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PRELIMINARY CY29351
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay
Features

Functional Description
The CY29351 is a low voltage high performance 200 MHz PLL-based zero delay buffer designed for high speed clock distribution applications. The CY29351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in four banks of one, one, two, and five outputs. Bank A divides the VCO output by two or four while the other banks divide by four or eight per SEL(A:D) settings (Table 3, "Function Table," on page 3). These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider (Table 2, "Frequency Table," on page 3). When PLL_EN# is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.
Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 2.5% max Output duty cycle variation 9 clock outputs: Drive up to 18 clock lines Two reference clock inputs: LVPECL or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9351 Industrial temperature range: -40C to +85C 32-pin 1.0-mm TQFP package
Block Diagram
SELA PLL_EN
REF_SEL TCLK PECL_CLK Phase Detector VCO 200 500 MHz /2 / /4 QA
LPF
/4 / /8
QB
FB_IN SELB SELC OE#
/4 / /8
QC0 QC1
/4 / /8 SELD
QD0 QD1 QD2 QD3 QD4
Cypress Semiconductor Corporation Document Number: 38-07475 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 21, 2008
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PRELIMINARY CY29351
Pinouts
Figure 1. Pin Diagram - 32 Pin TQFP Package
REF_SEL PLL_EN VDDQB 27 TCLK VSS VSS 25 QA 28 QB 26
32
31
30
29
A VD D F B _IN SE LA SE LB SELC SELD AVSS PEC L_C LK
1 2 3 4 5 6 7 8
C Y29351
24 23 22 21 20 19 18 17
QC0 VD D Q C QC1 VSS QD0 VD D Q D QD1 VSS
9
10
11
12
13
14 QD3
15 VDDQD
VDD
QD4
VSS
OE#
Table 1. Pin Definitions - 32 Pin TQFP Package Pin[1] Name IO Type 8 9 30 28 26 22, 24 2 10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 PECL_CLK TCLK QA QB QC(1,0) FB_IN OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS I, PU I, PD O O O O I, PD I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply PECL_CLK# I, PU/PD
PECL_CLK#
QD2
16
Description
LVPECL LVPECL reference clock input LVPECL LVPECL reference clock input. Weak pull up to VDD/2. LVCMOS LVCMOS/LVTTL reference clock input LVCMOS Clock output bank A LVCMOS Clock output bank B LVCMOS Clock output bank C LVCMOS Clock output bank D LVCMOS Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock LVCMOS Output enable/disable input LVCMOS PLL enable/disable input LVCMOS Reference select input LVCMOS Frequency select input, bank (A:D) VDD VDD VDD VDD VDD Ground Ground 2.5V or 3.3V power supply for bank B output clock[2,3] 2.5V or 3.3V power supply for bank C output clocks[2,3] 2.5V or 3.3V power supply for bank D output clocks[2,3] 2.5V or 3.3V power supply for PLL[5,6] 2.5V or 3.3V power supply for core, inputs, and bank A output clock[2,3] Analog ground Common ground
12, 14, 16, 18, 20 QD(4:0)
13, 17, 21, 25, 29 VSS
Notes 1. PU = Internal pull up, PD = Internal pull down. 2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins, the high-frequency filtering characteristics are cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins. 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 6. Inputs have pull up or pull down resistors that affect the input current.
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
Table 2. Frequency Table Feedback Output Divider /2 /4 /8 Table 3. Function Table Control REF_SEL PLL_EN OE# SELA SELB SELC SELD Default 0 1 0 0 0 0 0 PCLK Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs enabled / 2 (bank A) / 4 (bank B) / 4 (bank C) / 4 (bank D) 0 TCLK PLL enabled. The VCO output connects to the output dividers Outputs disabled (three-state), VCO running at its minimum frequency / 4 (bank A) / 8 (bank B) / 8 (bank C) / 8 (bank D) 1 VCO Input Clock * 2 Input Clock * 4 Input Clock * 8 Input Frequency Range (AVDD = 3.3V) 100 MHz to 200 MHz 50 MHz to 125 MHz 25 MHz to 62.5 MHz Input Frequency Range (AVDD = 2.5V) 100 MHz to 190 MHz 50 MHz to 95 MHz 25 MHz to 47.5 MHz
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC supply voltage DC operating voltage DC input voltage DC output voltage Output termination voltage Latch-up immunity Power supply ripple Temperature, storage Temperature, operating ambient Temperature, junction Dissipation, junction to case Dissipation, junction to ambient ESD protection (human body model) Failure in time Manufacturing test Functional Ripple frequency < 100 kHz Non Functional Functional Functional Functional Functional 2000 10 Functional Relative to VSS Relative to VSS Condition Min -0.3 2.375 -0.3 -0.3 - 200 - -65 -40 - 42 105 - Max 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 - 150 +150 +85 +150 Unit V V V V V mA mVp-p C C C C/W C/W Volts ppm
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
DC Electrical Specifications
(VDD = 2.5V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input voltage, low Input voltage, high Peak-Peak input voltage Common mode range[4] Output voltage, low[5] Output voltage, high[5] Input current, low[6] Input current, high[6] PLL supply current Quiescent supply current Dynamic supply current Input pin capacitance Output impedance LVCMOS LVCMOS LVPECL LVPECL IOL = 15mA IOH = -15mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded at 100 MHz Outputs loaded at 200 MHz Condition Min - 1.7 250 1.0 - 1.8 - - - - - - - 14 Typ. - - - - - - - - 5 - 180 210 4 18 Max 0.7 VDD+0.3 1000 VDD - 0.6 0.6 - -100 100 10 7 - - - 22 pF Unit V V mV V V V A A mA mA mA
DC Electrical Specifications
(VDD = 3.3V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input voltage, low Input voltage, high Peak-Peak input voltage Common mode range[4] Output Voltage, Low[5] Output voltage, high[5] Input current, low[6] Input current, high[6] PLL supply current Quiescent supply current Dynamic supply current Input pin capacitance Output impedance LVCMOS LVCMOS LVPECL LVPECL IOL = 24 mA IOL = 12 mA IOH = -24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded at 100 MHz Outputs loaded at 200 MHz Condition Min - 2.0 250 1.0 - - 2.4 - - - - - - - 12 Typ. - - - - - - - - - 5 - 270 300 4 15 Max 0.8 VDD + 0.3 1000 VDD - 0.6 0.55 0.30 - -100 100 10 7 - - - 18 pF V A A mA mA mA Unit V V mV V V
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
AC Electrical Specifications
(VDD = 2.5V 5%, TA = -40C to +85C)[7]
Parameter fVCO fin Description VCO frequency Input frequency /2 feedback /4 feedback /8 feedback Bypass mode (PLL_EN = 0) frefDC VPP VCMR tr , tf fMAX Input duty cycle Peak-Peak input voltage Common mode range[8] TCLK input rise/fall time Maximum output frequency LVPECL LVPECL 0.7V to 1.7V /2 output /4 output /8 output DC tr , tf t() tsk(O) tPLZ, HZ tPZL, ZH BW Output duty cycle Output rise/fall times fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V PCLK to FB_IN Output-to-Output skew Output disable time Output enable time PLL closed loop bandwidth (-3dB) /2 feedback /4 feedback /8 feedback tJIT(CC) tJIT(PER) tJIT() tLOCK Cycle-to-Cycle jitter Period jitter IO phase jitter Maximum PLL lock time Same frequency Multiple frequencies Same frequency Multiple frequencies Propagation delay (static phase offset) TCLK to FB_IN Condition Min 200 100 50 25 0 25 500 1.2 - 100 50 25 47.5 45 0.1 -100 -100 - - - - - - - - - - - - Typ. - - - - - - - - - - - - - - - - - - - - 2.2 0.85 0.6 - - - - 175 - Max 380 190 95 47.5 200 75 1000 VDD - 0.6 1.0 190 95 47.5 52.5 55 1.0 100 100 150 10 10 - - - 150 250 100 175 - 1 ps ms ps ps ps ns ns MHz ns ps % % mV V ns MHz Unit MHz MHz
Notes 7. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
AC Electrical Specifications
(VDD = 3.3V 5%, TA = -40C to +85C)[7]
Parameter fVCO fin Description VCO frequency Input frequency /2 feedback /4 feedback /8 feedback Bypass mode (PLL_EN = 0) frefDC VPP VCMR tr , tf fMAX Input duty cycle Peak-Peak input voltage Common mode range[8] TCLK input rise/fall time Maximum output frequency LVPECL LVPECL 0.8V to 2.0V /2 output /4 output /8 output DC tr , tf t() tsk(O) tsk(B) tPLZ, HZ tPZL, ZH BW Output duty cycle Output rise/fall times Propagation delay (static phase offset) Output-to-Output skew Bank-to-Bank skew Output disable time Output enable time PLL closed loop bandwidth (-3dB) /2 feedback /4 feedback /8 feedback tJIT(CC) tJIT(PER) tJIT() tLOCK Cycle-to-Cycle jitter Period jitter IO phase jitter Maximum PLL lock time Same frequency Multiple frequencies Same frequency Multiple frequencies IO same VDD fMAX < 100 MHz fMAX > 100 MHz 0.8V to 2.4V TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Banks at same voltage Banks at different voltages Condition Min 200 100 50 25 0 25 500 1.2 - 100 50 25 47.5 45 0.1 -100 -100 - - - - - - - - - - - - - Typ. - - - - - - - - - - - - - - - - - - - - - 2.2 0.85 0.6 - - - - 175 - Max 500 200 125 62.5 200 75 1000 VDD - 0.9 1.0 200 125 62.5 52.5 55 1.0 100 100 150 350 10 10 - - - 150 250 100 150 - 1 ps ms ps ps ps ps ns ns MHz ns ps % % mV V ns MHz Unit MHz MHz
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
Figure 2. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V
P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm
R T = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm D iffe re n tia l P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm R T = 50 ohm
VTT
VTT
Figure 4. LVPECL Propagation Delay t(f), static phase offset
PECL_CLK PECL_CLK
VPP
VCMR
VDD
FB_IN
VDD/2
t()
GND
Figure 5. LVCMOS Propagation Delay t(), static phase offset
VDD VDD/2 GND VDD
FB_IN
LVCMOS_CLK
VDD/2
t()
GND
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
Figure 6. Output Duty Cycle (DC)
VDD VDD/2
tP
T0
GND
DC = tP / T0 x 100%
Figure 7. Output-to-Output Skew, tsk(O)
VDD VDD/2 GND VDD VDD/2
tSK(O)
GND
Ordering Information
Part Number Pb-free CY29351AXI CY29351AXIT 32-pin TQFP 32-pin TQFP - tape and reel Industrial, -40C to 85C Industrial, -40C to 85C Package Type Product Flow
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
Package Drawing and Dimension
Figure 8. 32-Pin Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm
51-85063-*B
Document Number: 38-07475 Rev. *B
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PRELIMINARY CY29351
Document History Page
Document Title: CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Document Number: 38-0747 REV. ** *A *B ECN No. 128152 245448 2001108 Issue Date 07/07/03 See ECN See ECN Orig. of Change RGL RGL New Data Sheet Re-worded Select Function Descriptions in table 2. Description of Change
Corrected package thickness in Figure 7 from 1.4mm to 1.0mm. In Ordering PYG/KVM/AESA Information, removed leaded and added Pb-free parts.
(c) Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07475 Rev. *B
Revised January 21, 2008
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Spread AwareTM is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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